Phase change memory points comprise of a material which can change physical state under the effect of an electric signal, and more precisely under the effect of a temperature rise caused by an electric current passing through it (Joule effect). This state change is remnant and comes with a change in the electrical properties of the memory point. In a first so-called amorphous phase, the material has a high electrical resistivity, and in a second so-called crystalline phase the material has a low electrical resistivity.
Progress made in the compositions of phase change materials, for example chemical element-based alloys in column VI of the Mendeleyev table, such as tellurium Te or selenium Se, are such that the phase change can be obtained with a low-value voltage, for example in the order of 6V, and a current of a few hundred microamperes only, which enables phase change memory points to be integrated into the memories implanted onto semiconductor chips.
As an example, FIG. 1 represents the architecture of a memory array MA of the type described by EP 1 450 373. The memory array MA comprises memory cells CELi,j,k arranged as a matrix and each linked to a word line WLi of rank i and to a bit line BLjk of rank j (j ranging from 0 to m) belonging to a column COLk of rank k. Each memory cell CELi,j,k comprises a selection transistor TS, for example an NMOS transistor, and a phase change memory point P. The anode of the memory point P is linked to a bit line BLjk and its cathode is linked to the ground (or to a switchable ground line) through the selection transistor TS. The gate terminal of the transistor TS is linked to a word line WLi.
As shown in FIG. 2, the memory point P has two stable states SET and RST (short for “RESET”) corresponding to the two abovementioned types of resistivity. In the state SET which corresponds for example to the storing of a logic “0”, the memory point has a first series resistance, for example 5 to 10 K ohms, while in the state RST corresponding to the storing of a logic “1”, the memory point has a second series resistance, for example 100 to 200 K ohms.
The change from the state SET to the state RST (erasing) is ensured by applying to the memory point a voltage pulse RPULSE of the type represented in FIG. 3A, having a voltage plateau Vp of a duration in the order of 100 nanoseconds for example, and a very fast fall time Tq1 in the order of a few nanoseconds. The voltage Vp and the relevant current (a few hundred microamperes) cause a warming by Joule effect which renders the material amorphous (RST state). The change from the state RST to the state SET (programming) is ensured by applying to the memory point a voltage pulse SPULSE of the type represented in FIG. 3B, having a voltage plateau Vp of a duration in the order of 50 nanoseconds for example, and a long fall time Tq2 in the order of 300 nanoseconds for example. The effect of applying such a voltage ramp of duration Tq2 is to have the material recrystallized, while on the contrary the fall time Tq1 of the pulse RPULSE must be very short to prevent the recrystallization.
Reading the memory point P makes it possible to determine whether the latter has the first or the second series resistance. Such a reading is conducted under a low voltage so as not to modify the state of the memory point by causing a spurious erase or programming. For a better understanding, it is accepted that a read voltage Vr in the order of 0.5 V, lower than the threshold voltage of a MOS transistor (generally in the order of 0.7 V), is low enough not to cause a state change in a memory point that is in the erased or programmed state.
The integration of phase change memory points into a CMOS memory on a silicon substrate is an objective for this memory technology to be industrially used, due to the low cost price of CMOS integrated circuits. They comprise transistors of a first type of conductivity and transistors of a second type of conductivity, generally referred to as PMOS and NMOS transistors.
Moreover, the fact that it is possible to erase or program the memory cells with a voltage Vp in the order of 6 V enables a memory devoid of any high-voltage transistors to be envisaged, contrary to FLASH or EEPROM memories using high-voltage floating-gate transistors to control a high erase or programming voltage Vpp in the order of 10 to 15 V.
However, the voltage Vp is close to the maximum voltage that a low-voltage transistor can bear, or “maximum technological voltage Vmax”, or even equal to this maximum voltage.
Thus, it is desirable to produce a CMOS technology memory whereby an erase or programming voltage Vp which is close or equal to the maximum technological voltage of the memory can be applied to phase change memory cells, without using any high-voltage transistor.
It is also desirable to be able to apply a low-value read voltage Vr to memory cells, using application means that are simple in structure and inexpensive to produce.
Now, the CMOS memory structures according to prior art do not enable these objectives to be achieved. This will be understood with reference to FIG. 4 which represents a memory architecture of the type described by the application EP 1 450 373. The memory comprises a memory array MA and phase change memory cells of the type described above. The memory also comprises a column selection circuit CSEL1 connected to the bit lines BLjk of the memory array (the bit lines represented being lines BL0k to BLmk of a same column COLk). The selection circuit CSEL1 comprises bit line selection blocks Bjk (B0k . . . Bmk) with one block per bit line. Each selection block comprises in series two transistors TP1, TP2 of PMOS type and one transistor TN1 of NMOS type. The gate terminals of these transistors are controlled by selection signals YMk, YNk, YOk supplied by a column decoder CDEC1. The gate terminal of the transistor TP1 receives the signal YMk, the gate terminal of the transistor TP2 receives the signal YNk and the gate terminal of the transistor TN1 receives the signal YOk.
During phases of erasing or programming memory cells, the voltage Vp is supplied by erase or programming latches PLTj (PLT0-PLTm) and is applied to the bit lines through the selection transistors TP1, TP2, TN1. For this purpose, the signals YM and YN are set to 0 (ground of the circuit) while the signal YO must be taken to a gate voltage at least equal to Vp+Vth+Vb so that the voltage Vp is transferred without loss, Vth being the threshold voltage of the MOS transistors and Vb the body effect voltage.
Thus, a first disadvantage of this classic memory is that the signal YO must be boosted. If the voltage Vp is equal to the maximum technological voltage Vmax, the supply of the signal YO equal to Vp+Vth+Vb (i.e., Vmax+Vth+Vb) is not possible or requires high-voltage transistors in the column decoder CDEC1 as well as a charge pump (booster circuit) to supply the voltage Vp+Vth+Vb.
During phases of reading memory cells, sense amplifiers SAMPj (SAMP0-SAMPm) supply a voltage Vbl which is applied to the bit lines through the selection transistors TP1, TP2, TN1. This voltage is limited by the transistor TN1 by adjusting the gate voltage of this transistor in the vicinity of the value Vr+Vth+Vb, so that the memory cells only receive the read voltage Vr. Now, an accurate control of the voltage level of the selection signal YO is incompatible with the production of a column decoder that is simple in structure and inexpensive, delivering binary signals.
Another known solution to read a phase change memory point involves using a sense amplifier supplying a read voltage Vbl equal to Vr, for example a sense amplifier as described in the application PCT/FR2006/001686. However, in this case, the read voltage Vr, for example 0.5 V, must be able to be transferred without attenuation by the transistors TP1, TP2, TN1. This requires taking the signals YM, YN which control the gate terminals of the transistors TP1, TP2 to a negative value equal to or lower than −(Vth+Vp) Negative voltage charge pumps must thus be provided, which further complicates the architecture of the column decoder CDEC1. The gate terminals of isolation transistors TI which link the erase or programming latches to the bit lines must also receive a negative voltage.